PIC16C63A-04I/SO【PDF 77/184 页】IC MCU OTP 4KX14 PWM 28SOIC

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168

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

23.7.3.2

Interrupt Nesting

The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service

of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the inter-

rupt at the processor level.

When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is

re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt

service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed

into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing

is finished and the AIC_EOICR is written.

The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant

to having eight priority levels.

23.7.3.3

Interrupt Vectoring

The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1

to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register),

the value written into AIC_SVR corresponding to the current interrupt is returned.

This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as

AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at

address 0x0000 0018 through the following instruction:

LDR

PC,[PC,# -&F20]

When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus

branching the execution on the correct interrupt handler.

This feature is often not used when the application is based on an operating system (either real time or not). Oper-

ating systems often have a single entry point for all the interrupts and the first task performed is to discern the

source of the interrupt.

However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt

vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operat-

ing system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt

to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt han-

dler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software

peripheral handling) to be handled efficiently and independently of the application running under an operating

system.

23.7.3.4

Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the

programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and

the associated status bits.

It is assumed that:

The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corre-

sponding interrupt service routine addresses and interrupts are enabled.

The instruction at the ARM interrupt exception vector address is required to work with the vectoring

LDR PC, [PC, # -&F20]

When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:

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